Memtest86 is considered by the majority of the hardware testing community the number one application when it comes to defective RAM sticks. The answer to the question regarding the working state of the installed memory modules comes fast with Memtest86 and that is what matters the most besides the certainty of the verdict.
There are many good approaches for testing memory. However, many tests simply throw some patterns at memory without much thought or knowledge of memory architecture or how errors can best be detected. This works fine for hard memory failures but does little to find intermittent errors. BIOS based memory tests are useless for finding intermittent memory errors.
RAM chips consist of a large array of tightly packed memory cells, one for each bit of data. The vast majority of the intermittent failures are a result of interaction between these memory cells. Often writing a memory cell can cause one of the adjacent cells to be written with the same data. An effective memory test attempts to test for this condition. Therefore, an ideal strategy for testing memory would be the following:
- Write a cell with a zero.
- Write all of the adjacent cells with a one, one or more times.
- Check that the first cell still has a zero.
It should be obvious that this strategy requires an exact knowledge of how the memory cells are laid out on the chip. In addition there are a never ending number of possible chip layouts for different chip types and manufacturers making this strategy impractical. However, there are testing algorithms that can approximate this ideal and MemTest86 does just this.
• CPU cores that are identified as hyperthreads are now disabled by default, due to minimal performance benefits
• Fixed potential system hang caused by memory alignment issues when allocating 128-bit variables on the stack during the 128-bit random number sequence test (Test 12)
• Improved performance of the 128-bit random number sequence test (Test 12) by using SSE2 comparison intrinsics
• Improved performance of the row hammer test (Test 13) by increasing the default step size to 0x1000000 (16MB) for subsequent passes after the first pass. On the first pass, the default step size is 0x4000000 (64MB)
• Reduced test time of the row hammer test (Test 13) by using only a single offset bit to determine the row address pair, rather than cycle through all possible offset bits.
• Added ‘ENABLEHT’ config file parameter to enable/disable CPU cores identified as hyperthreads
• Added ‘HAMMERSTEP’ config file parameter to specify the step size for the next row pair to hammer in the row hammer test (Test 13). Increasing the step size reduces the memory test coverage, but will also decrease the test time. By default, the step size is 0x1000000 (16MB)
• Added several known baseboards to to a ‘blacklist’ of boards that have known issues when running in multiprocessor mode. If a blacklisted baseboard is detected, the Multiprocessor test is skipped during startup and the CPU selection mode is set to single.
• Fixed triggering of ECC error injection on Intel Skylake (Xeon E3 v5) chipset
• Added ECC detection and injection support for Intel KabyLake (Xeon E3 v6 family) chipsets
• Added ECC detection and injection support for Apollo Lake SoC (Atom E3900 Series) chipsets
• Added support for retrieving RAM SPD data on Intel Skylake-E chipsets
• Fixed issue with the test elapsed time having strange values when running in round robin or sequential CPU mode due to the timestamp counter not being synchronized on the CPU cores